Duration: 3 MONTHS

Course Syllabus

  • Introduction to VHDLdesign units, data objects, signal drivers, inertial and transport delays, delta delay, VHDL data types, concurrent and sequential statements.
  • Subprograms - Functions, Procedures, attributes, generio, generate, package, IEEE standard logic library, file I/O, test bench, component declaration, instantiation, configuration.
  • Computational logic circuit design and VHDL implementation of following circuits - first adder, Sub-tractor, decoder, encoder, multiplexer, ALU, barrel shifter, 4X4 key board encoder, multiplier, divider, Hamming code encoder and correction circuits.
  • Synchronous sequential circuits design - finite state machines, Mealy and Moore, state assignments, design and VHDL implementation of FSMs, Linear feedback shift register (Pseudo random and CRC)
  • Asynchronous sequential circuit design - primitive flow table, concept of race, critical race and hazards, design issues like meta stability, synchronizes, clock skew and timing considerations.
  • Introduction to place & route process- Introduction to ROM, PLA, PAL, Architecture of CPLD (Xilinx / Altera)

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